Clock and data recovery (CDR) systems have been implemented to align a sample clock with a data stream.
Where a sample rate of approximately 4 GHz is utilized, adjustment step sizes of approximately 2 pico seconds (ps) may be desirable.
A CDR may include a phase interpolator to interpolate between multiple phases of a reference clock, to generate a sample clock that is approximately aligned with a data stream.
Conventional CDR systems utilize phase interpolators to interpolate between clock phases that are relatively widely spaced, such as 90°. Phase interpolators designed to provide relatively fine resolution or step sizes from relatively widely spaced reference clock phases consume relatively significant amounts of power and area. A contention based phase interpolator may consume less power than other types of phase interpolators, but cannot interpolate well between relatively widely spaced clocks, which results in relatively poor linearity.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.